1. Field of the Invention
The present invention relates to an integrated circuit (IC), and more particularly to an overlay mark used for alignment accuracy measurement in an IC.
2. Description of the Prior Art
As the linewidth of the IC process continuously gets narrower, the alignment accuracy between a lower layer and an upper layer becomes more and more important. Therefore, an overlay mark is generally formed on a wafer to check alignment accuracy.
A conventional overlay mark typically includes x-directional linear patterns and y-directional linear patterns of a single pre-layer, and x-directional linear patterns and y-directional linear patterns of the current layer. Overlay errors have been measured only between two adjacent layers.
However, in ICs with multiple layers, displacement between non-adjacent layers may compromise IC performance. Therefore, improving the integrity of overlay marks between multiple pre-layers is still an important issue in the field.